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Hardware description languages
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161	C-based High Level Synthesis and Verification Tool Set for ASIC・FPGA C-based Design Enables Higher Design Efficiency, Lower Area and Higher Performance of Your Chip (compared to RTL-based design) Add to Reading List Source URL: www.nec.com Language: English - Date: 2012-12-26 01:09:09 Hardware verification languages Logic design SystemC High-level synthesis Logic synthesis VHDL Verilog Field-programmable gate array Logic simulation Electronic engineering Electronic design automation Hardware description languages
162	Available online at www.sciencedirect.com Procedia Computer Science[removed] – 54 Proceedings of the 3rd International Conference on Computational Systems-Biology and Bioinformatics (CSBio 2012) Add to Reading List Source URL: www.openwetware.org Language: English - Date: 2012-12-12 14:13:55 Electronics Flip-flop Electrical engineering Hardware description languages Counter Verilog Logic gate Sequential logic Random-access memory Digital electronics Electronic engineering Computer memory
163	SNPS[removed]10-K Add to Reading List Source URL: synopsys.com Language: English - Date: 2014-12-15 13:24:22 Integrated circuits Hardware verification languages Synopsys Hardware description language Electronic system-level design and verification Signoff Logic synthesis Integrated circuit design SystemVerilog Electronic engineering Electronic design automation Electronic design
164	COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Ou Add to Reading List Source URL: dcd.pl Language: English - Date: 2014-10-23 09:06:18 Data transmission Universal asynchronous receiver/transmitter Embedded systems Microcontrollers 16550 UART VHDL Verilog COM Field-programmable gate array Electronic engineering Electronics Hardware description languages
165	SynaptiCAD Big Feature List SynaptiCAD was founded in 1992 to provide affordable high quality timing diagram editing tools. Since that time we have expanded our product line to include: VHDL & Verilog test bench generati Add to Reading List Source URL: www.syncad.com Language: English - Date: 2011-04-06 10:25:45 Verilog VHDL Waveform viewer Logic analyzer Field-programmable gate array Jitter Aldec Phase-locked loop Static timing analysis Electronic engineering Electronics Hardware description languages
166	Using Separation of Concerns for Embedded Systems Design ∗ Ethan K. Jackson Janos Sztipanovits Add to Reading List Source URL: www.isis.vanderbilt.edu Language: English - Date: 2008-06-17 13:30:56 Electronics Hardware description languages Computer architecture Concurrent computing Computer data Dataflow Denotational semantics SIGNAL Topology Computing Models of computation Software engineering
167	Available online at www.sciencedirect.com Procedia Computer Science[removed] – 54 Proceedings of the 3rd International Conference on Computational Systems-Biology and Bioinformatics (CSBio 2012) Add to Reading List Source URL: openwetware.org Language: English - Date: 2012-12-12 14:13:55 Electronics Flip-flop Electrical engineering Hardware description languages Counter Verilog Logic gate Sequential logic Random-access memory Digital electronics Electronic engineering Computer memory
168	F R A U N H O F E R I N S T I T U T E F O R I N T E G R AT E D C I R C U I T S I I S D E S I G N A U T O M AT I O N D I V I S I O N E A S © Alexandr Mitiuc - Fotolia.com SERVICES AND DESIGN Add to Reading List Source URL: www.eas.iis.fraunhofer.de Language: English - Date: 2015-01-16 02:39:01 SystemC Transaction-level modeling Esterel Studio Electronic engineering Electronic design automation Hardware description languages
169	SNPS[removed]10-K Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-24 17:15:56 Integrated circuits Hardware verification languages Synopsys Hardware description language Electronic system-level design and verification Signoff Logic synthesis Integrated circuit design SystemVerilog Electronic engineering Electronic design automation Electronic design
170	F R A U N H O F E R I N S T I T U T e for integrated circuits I I S design automation di v ision E A S Photo: Jürgen Lösel Coside® – Add to Reading List Source URL: www.eas.iis.fraunhofer.de Language: English - Date: 2015-01-15 11:33:57 Hardware description languages SystemC Catapult C Electronic engineering Electronic design automation Hardware verification languages

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